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? semiconductor components industries, llc, 2016 march, 2016 ? rev. 3 1 publication order number: kac?06040/d kac-06040 2832 (h) x 2128 (v) cmos image sensor description the kac?06040 image sensor is a high-speed 6 megapixel cmos image sensor in a 1 optical format based on a 4.7 m 5t cmos platform. the image sensor features very fast frame rate, excellent nir sensitivity, and flexible readout modes with multiple regions of interest (roi). the readout architecture enables use of 8, 4, or 2 lvds output banks for full resolution readout of 160 frames per second. each lvds output bank consists of up to 8 differential pairs operating at 200 mhz ddr for a 400 mbps data rate per pair. the pixel architecture allows rolling shutter operation for motion capture with optimized dynamic range or global shutter for precise still image capture. table 1. general specifications parameter typical value architecture 5t global shutter cmos resolution 6 megapixels aspect ratio 4:3 pixel size 4.7 m (h) 4.7 m (v) total number of pixels 3024 (h) 2320 (v) number of effective pixels 2848 (h) 2144 (v) number of active pixels 2832 (h) 2128 (v) active image size 13.1 mm (h) 10.0 mm (v) 16.65 mm (diag.), 1 optical format master clock input speed 5 mhz to 50 mhz maximum pixel clock speed 200 mhz ddr lvds, 400 mbps number of lvds outputs 64 differential pairs number of output banks 8, 4, or 2 frame rate, 6 mp 1?160 fps 10 bits charge capacity 17,000 electrons quantum efficiency kac?06040?cba kac?06040?aba 40%, 47%, 45% (470, 540, 620 nm) 53%, 15%, 10% (500, 850, 900 nm) read noise (at maximum lvds clock) 3.4 e ? rms, rolling shutter 25 e ? rms, global shutter dynamic range 74 db, rolling shutter 57 db, global shutter blooming suppression > 10,000x image lag 1.6 electron digital core supply 2.0 v analog core supply 1.8 v pixel supply 2.8 v & 3.5 v power consumption 2.3 w for 6 mp @ 160 fps 10 bits package 267 pin ceramic micro-pga cover glass ar coated, 2-sides note: all parameters are specified at t = 40 c unless otherwise noted. www.onsemi.com figure 1. kac?06040 cmos image sensor features ? global shutter and rolling shutter ? very fast frame rate ? high nir sensitivity ? multiple regions of interest ? interspersed video streams application ? machine vision ? intelligent transportation systems ? surveillance see detailed ordering and shipping information on page 2 o f this data sheet. ordering information
kac?06040 www.onsemi.com 2 the image sensor has a pre-configured qhd (4 720p, 16:9) video mode, fully programmable, multiple roi for windowing, programmable sub-sampling, and reverse readout (flip and mirror). the two adcs can be configured for 8-bit, 10-bit, 12-bit or 14-bit conversion and output. additional features include interspersed video streams (dual-video), on-chip responsivity calibration, black clamping, overflow pixel for blooming reduction, black-sun correction (anti-eclipse), column and row noise correction, and integrated timing generation with spi control, 4:1 and 9:1 averaging decimation modes. ordering information table 2. ordering information ? kac?06040 image sensor part number description marking code kac?06040?aba?jd?ba monochrome, micro-pga package, sealed clear cover glass with ar coating (both sides), standard grade. kac?06040?aba serial number kac?06040?aba?jd?ae monochrome, micro-pga package, sealed clear cover glass with ar coating (both sides), engineering grade. kac?06040?cba?jd?ba bayer (rgb) color filter pattern, micro-pga package, sealed clear cover glass with ar coating (both sides), standard grade. kac?06040?cba serial number kac?06040?cba?jd?ae bayer (rgb) color filter pattern, micro-pga package, sealed clear cover glass with ar coating (both sides), engineering grade. 1. engineering grade samples might not meet final production testing limits, especially for cosmetic defects such as clusters, but also possib ly column and row artifacts. overall performance is representative of final production parts. table 3. ordering information ? evaluation support part number description kac?06040?ab?a?gevk evaluation hardware for kac?06040 image sensor (bayer). includes image sensor. kac?06040?cb?a?gevk evaluation hardware for kac?06040 image sensor (monochrome). includes image sensor. lens?mount?kit?c?gevk lens mount kit that supports c, cs, and f mount lenses. includes ir cut-filter for color imaging. see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com .
kac?06040 www.onsemi.com 3 device description architecture figure 2. block diagram g b g r 4000 (h) 3000 (v) 4.7 m pixel g b g r g b g r g b g r lvds bank 2 lvds bank 4 lvds bank 6 even row adc, analog gain, black-sun correction clk2 clk4 clk6 2d 0 ? 2d 6 4d 0 ? 4d 6 6d 0 ? 6d 6 8 88 8 88 odd row adc, analog gain, black-sun correction lvds bank 3 lvds bank 5 lvds bank 7 (0, 0) clk7 7d 0 ? 7d 6 clk5 5d 0 ? 5d 6 clk3 3d 0 ? 3d 6 lvds bank 0 lvds bank 1 digital gain/offset, noise correction clk1 1d 0 ? 1d 6 clk0 0d 0 ? 0d 6 timing control, sub-sampling/averaging 8 104 8 104 3.5 v a 3.3 v d 2.8 v a 2.0 v d 1.8 v a chip clock trigger resetn csn sclk mosi miso serial peripheral interface (spi) adc_ref1 adc_ref2 vss 0 v 4.02 k 1% rbfb
kac?06040 www.onsemi.com 4 physical orientation figure 3. package pin orientation ? top x-ray view lvds bank 2 lvds bank 4 lvds bank 6 lvds bank 3 lvds bank 5 lvds bank 7 lvds bank 0 lvds bank 1 a b c d e aa ab ac ad ae 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1. the center of the pixel array is aligned to the physical package center. 2. the region under the sensor die is clear of pins enabling the use of a heat sink. 3. non-symmetric mounting holes provide orientation and mounting precision. 4. non-symmetric pins prevent incorrect placement in pcb. 5. letter ?f? indicator shows default readout direction relative to package pin 1. notes:
kac?06040 www.onsemi.com 5 table 4. primary pin description pin name type description ab09 resetn di sensor reset (0 v = reset state) e07 clk_in1 di sensor input clk_in1 (5?50 mhz) d08 clk_in2 di sensor input clk_in2 (connect to clk1) ab08 trigger di trigger input (optional) aa05 sclk di spi master clock aa06 csn di spi chip select (0 v = selected) aa07 miso do spi master input, slave output aa08 mosi di spi master output, slave input ab05 fb do spi register read feedback d07 spi_ms di spi cpol/cpha mode select aa14 adc_ref1 ao 4.02 k 1% resistor between ref1 & ref2 aa15 adc_ref2 ao 4.02 k 1% resistor between ref1 & ref2 ab06 flo do flash output sync (optional) ab07 mso do mechanical shutter output sync (optional) e05 fen do frame enable reference output (optional) e06 len do line enable reference output (optional) 1. di = digital input, do = digital output, ao = analog output. 2. tie unused di pins to ground, no connect (nc) unused do pins. 3. by default clk_in2 should equal clk_in1 and should be the same source clock. 4. the resetn pin has a 62 k internal pull-up resistor, so if left floating the chip will not be in reset mode. 5. the trigger pin has an internal 100 k pull down resistor. if left floating (and at default polarity) then the sensor state will not be af fected by this pin (i.e. defaults to ?not triggered? mode if floated). 6. all of the di and do pins nominally operate at 0 v 2.0 v and are associated with the vdd_dig power supply. 7. the spi_ms pin has an internal 100 k pull down resistor. if left floating the cpol/chpa will be compatible with cpol = cpha = 0 or cpol = cpha = 1. table 5. power pin description name voltage pins description vdd_lvds 3.3 v d c04, c05, c23, c24, d04, d24, e04, e24, aa04, aa24, ab04, ab24, ac04, ac05 ac23, ac24 lvds output supply vdd_dig 2.0 v d c18, c19, c20, c21, c22, d18, d19, d20, d21, d22, d23, e08, e18, e20, e21, e22, aa18, aa20, aa21, aa22, ab18, ab19, ab20, ab21, ab22, ab23, ac18, ac19, ac20, ac21, ac22, ab15 digital core supply avdd_hv 3.5 v a c11, d11, e11, aa11, ab11, ac11, c10, d10, e10, aa10, ab10, ac10 pixel supply 1 vref_p 2.8 v a c13, d13, e13, aa13, ab13, ac13 pixel supply 2 avdd_lv 1.8 v a c17, d16, d17, e17, aa17, ab16, ab17, ac17 analog low voltage supply vpixel_low 0 v e09 pixel supply 3. combine with vss for normal operation. can be pulsed for extended dynamic range operation. vss 0 v a02, a14, a26, b14, c03, c06, c12, c14, c25, d03, d12, d14, d25, e03, e12, e19, e23, e25, aa03, aa12, aa19, aa23, aa25, ab03, ab12, ab14, ab25, ac03, ac06, ac12, ac14, ac25, ad14, ae02, ae14, ae26, d15, e15, aa09 sensor ground reference no connect na a01, e14, e16, c09, d09, d05, d06, aa16, ac09 unused and test-only pins. these pins must be floated.
kac?06040 www.onsemi.com 6 pin name description e01 1dclk+ e02 1dclk? d01 1data0+ d02 1data0? c01 1data1+ c02 1data1? b01 1data2+ b02 1data2? a03 1data3+ b03 1data3? a04 1data4+ b04 1data4? a05 1data5+ b05 1data5? a06 1data6+ b06 1data6? bank 1 lvds clock bank 1 lvds data pin name description c07 3dclk+ c08 3dclk? a07 3data0+ b07 3data0? a08 3data1+ b08 3data1? a09 3data2+ b09 3data2? a10 3data3+ b10 3data3? a11 3data4+ b11 3data4? a12 3data5+ b12 3data5? a13 3data6+ b13 3data6? bank 3 lvds clock bank 3 lvds data pin name description c15 5dclk+ c16 5dclk? a15 5data0+ b15 5data0? a16 5data1+ b16 5data1? a17 5data2+ b17 5data2? a18 5data3+ b18 5data3? a19 5data4+ b19 5data4? a20 5data5+ b20 5data5? a21 5data6+ b21 5data6? bank 5 lvds clock bank 5 lvds data pin name description a22 7dclk+ b22 7dclk? a23 7data0+ b23 7data0? a24 7data1+ b24 7data1? a25 7data2+ b25 7data2? b27 7data3+ b26 7data3? c27 7data4+ c26 7data4? d27 7data5+ d26 7data5? e27 7data6+ e26 7data6? bank 7 lvds clock bank 7 lvds data pin name description aa01 0dclk+ aa02 0dclk? ab01 0data0+ ab02 0data0? ac01 0data1+ ac02 0data1? ad01 0data2+ ad02 0data2? ae03 0data3+ ad03 0data3? ae04 0data4+ ad04 0data4? ae05 0data5+ ad05 0data5? ae06 0data6+ ad06 0data6? bank 0 lvds clock bank 0 lvds data pin name description ac07 2dclk+ ac08 2dclk? ae07 2data0+ ad07 2data0? ae08 2data1+ ad08 2data1? ae09 2data2+ ad09 2data2? ae10 2data3+ ad10 2data3? ae11 2data4+ ad11 2data4? ae12 2data5+ ad12 2data5? ae13 2data6+ ad13 2data6? bank 2 lvds clock bank 2 lvds data pin name description ac15 4dclk+ ac16 4dclk? ae15 4data0+ ad15 4data0? ae16 4data1+ ad16 4data1? ae17 4data2+ ad17 4data2? ae18 4data3+ ad18 4data3? ae19 4data4+ ad19 4data4? ae20 4data5+ ad20 4data5? ae21 4data6+ ad21 4data6? bank 4 lvds clock bank 4 lvds data pin name description ae22 6dclk+ ad22 6dclk? ae23 6data0+ ad23 6data0? ae24 6data1+ ad24 6data1? ae25 6data2+ ad25 6data2? ad26 6data3+ ad27 6data3? ac26 6data4+ ac27 6data4? ab26 6data5+ ab27 6data5? aa26 6data6+ aa27 6data6? bank 6 lvds clock bank 6 lvds data 1. all lvds data and clock lines must be routed with 100 differential transmission line traces. 2. all the traces for a single lvds bank should be the same physical length to minimize skew between the clock and data lines. 3. in 2 bank mode, only lvds banks 0 and 1 are active. 4. in 4 bank mode, only lvds bank 0, 1, 2, and 3 are active. 5. float the pins of unused lvds banks to conserve power. 6. unused pins in active banks (due to adc bit depth < 14) are automatically tri-stated to save power, but these can also be floa ted. table 6. lvds pin description
kac?06040 www.onsemi.com 7 imaging performance table 7. typical operational conditions (unless otherwise noted, the imaging performance specifications are measured using the following conditions.) description condition notes light source continuous red, green and blue led illumination 1 temperature measured die temperature: 40 c and 27 c integration time 16.6 ms (1400d ll, register 0201h) readout mode dual-scan, global shutter, 320 mhz, pll2 clamps column/row noise correction active, frame black level clamp active adc bit depth 10 bit analog gain unity gain or referred back to unity gain 1. for monochrome sensor, only green led used. table 8. kac?12040?aba configuration (monochrome) description symbol wavelength (nm) nom. units sampling plan temperature tested at ( c) test peak quantum efficiency green nir1 nir2 qe max 550 850 900 52 15 9.0 % design 27 responsivity 83 ke lux s design 27 20 responsivity 7.3 v lux s design 27 21 table 9. kac?12040?cba configuration (bayer rgb) description symbol wavelength (nm) nom. units sampling plan temperature tested at ( c) test peak quantum efficiency green nir1 nir2 qe max 470 540 620 850 900 42 47 44 16 9.8 % design 27 responsivity blue green red 18 36 39 ke lux s design 27 20 responsivity blue green red 1.6 3.1 3.4 v lux s design 27 21
kac?06040 www.onsemi.com 8 table 10. performance specifications all configurations description symbol min nom. max units sampling plan temperature tested at ( c) test notes photodiode charge capacity pne 17 ke ? die 27, 40 16 read noise ne ? t 3.4 rs/gr ds 3.7 rs/gr ts 25 gs ds/ts e ? rms die 27 8 total pixelized noise tpn 3.6 rs/gr ds 3.9 rs/gr ts 25 gs ds/ts e ? rms die 27 19 dynamic range dr 74 rs/gr ds 73 rs/gr ts 57 gs ds/ts db die 27 3 column noise c n 0.4 rs/gr ds/ts 2.4 gs ds/ts e ? rms die 27 9 5 row noise r n 0.4 rs/gr ds 0.7 rs/gr ts 2.7 gs ds/ts e ? rms die 27 10 6 dark field local non-uniformity floor dsnu_flr 1.3 rs/gr ds 1.7 rs/gr ts 10 gs ds/ts e ? rms die 27, 40 1 4 bright field local photoresponse non-uniformity prnu_1 1.1 mono 1.5 bayer % rms die 27, 40 2 1 bright field global photoresponse non-uniformity prnu_2 3.7 mono 3.4 bayer % pp die 27, 40 3 1 maximum photoresponse non-linearity nl 5.4 % die 27, 40 11 2 maximum gain difference between outputs g 0.3 % die 27, 40 12 7 photodiode dark current i pd 6.6 e/p/s die 40 13 8 storage node dark current i vd 1490 e/p/s die 40 14 4 image lag lag 1.6 e ? design 27, 40 15 black-sun anti-blooming x ab 15 > 10,000 w/cm 2 xllumsat design 27 7 13 parasitic light sensitivity pls 728 design 27 6 9 dual-video wdr 140 rs 120 gs db design 27 10, 11 pulsed pixel wdr (gs only) 100 db design 27 12, 11 note: rs = rolling shutter operation mode, gs = global shutter operation mode, gr = global reset, ds = dual?scan, ts = tri?scan 1. measured per color, worst of all colors reported. 2. value is over the range of 10% to 90% of photodiode saturation, green response used. 3. uses 20log (pne / ne ? t). 4. photodiode dark current made negligible. 5. column noise correction active. 6. row noise correction active. 7. measured at 70% illumination. 8. storage node dark current made negligible. 9. gse (global shutter efficiency) = 1 ? 1 / pls. 10. min vs max integration time at 30 fps. 11. wdr measures expanded exposure latitude from linear mode dr. 12. min/max responsivity in a 30 fps image. 13. saturation illumination referenced to a 3 line time integration.
kac?06040 www.onsemi.com 9 typical performance curves monochrome with microlens figure 4. monochrome qe (with microlens) color (bayer rgb) with microlens figure 5. bayer qe (with microlens)
kac?06040 www.onsemi.com 10 angular quantum efficiency for the curves marked ?horizontal?, the incident light angle is varied along the wider array dimension. for the curves marked ?vertical?, the incident light angle is varied along the shorter array dimension. figure 6. monochrome relative angular qe (with microlens) figure 7. bayer relative angular qe (with microlens)
kac?06040 www.onsemi.com 11 dark current vs. temperature figure 8. dark current vs. temperature note: ?dbl? denotes an approximate doubling temperature for the dark current for the displayed temperature range. power vs. frame rate the most effective method to set the frame rate is to use vertical blanking (register 01f1h). unnecessary chip operations are suspended during vertical blanking conserving significant power consumption and also minimizing the image storage time on the storage node when in global shutter operation. tri?scan can reach higher frame rates, but consumes more power at all frame rates. it is recommended use dual?scan unless the frame rate required can only be reached with tri?scan. the lvds clock is 1/2 the pll2 clock frequency. figure 9. dual?scan power vs. frame rate, 10 bit mode
kac?06040 www.onsemi.com 12 figure 10. tri?scan power vs. frame rate, 10 bit mode power and frame rate vs. adc bit depth increasing the adc bit depth impacts the frame rate by changing the adc conversion time. the following figure shows the power and frame rate range for several typical cases. for optimum image quality and power consumption the pll2 and vertical blanking have been optimized for each bit depth and target frame rate. because of the dif ferent parameters impacting the line time, tri?scan only has significant benefit at 10 bit operation. at 8 bit operation the lvds readout time dominates the line time; and at 12 and 14 bit the adc time dominates the line time and the pixel time is not significant. but at 10 bit operation tri?scan can almost halve the line time at the cost of additional power consumption. figure 11. dual?scan adc bit depth impact on frame rate and power
kac?06040 www.onsemi.com 13 figure 12. tri?scan vs. dual?scan power
kac?06040 www.onsemi.com 14 defect definitions table 11. operation conditions for defect testing description condition notes operational mode 10 bit adc, 8 lvds outputs, global shutter and rolling shutter modes, dual?scan, black level clamp on, column/row noise correction on, 1x analog gain, 1x digital gain pixels per line 2832 lines per frame 2128 line time 6.875 s frame time 8.25 ms photodiode integration time 33 ms storage readout time 7.85 ms temperature 40 c and 30 c light source continuous red, green and blue led illumination (green only for monochrome sensor) operation nominal operating voltages and timing, pll1 = 320 mhz, pll2 = 410 mhz table 12. defect definitions for testing description definition limit test notes dark field defective pixel 30 c rs: defect 20 dn gs: defect 180 dn 40 c rs: defect 30 dn gs: defect 240 dn 60 4 1, 4, 5 bright field defective pixel defect 12% from local mean 60 5 2, 5 cluster defect a group of 2 to 10 contiguous defective pixels, but no more than 3 adjacent defects horizontally. 11 3 column/row major defect a group of more than 10 contiguous defective pixels along a single column or row. 0 dark field faint column/row defect rs: 3 dn threshold gs: 10 dn threshold 0 17 1 bright field faint column/row defect rs: 12 dn threshold gs: 18 dn threshold 0 18 1 1. rs = rolling shutter, gs = global shutter. 2. for the color devices, all bright defects are defined within a single color plane, each color plane is tested. 3. cluster defects are separated by no less than two good pixels in any direction. 4. rolling shutter dark field points are dominated by photodiode integration time, global shutter dark field defects are dominat ed by the readout time. 5. the net sum of all bright and dark field pixel defects in rolling and global shutter are combined and then compared to the te st limit.
kac?06040 www.onsemi.com 15 test definitions test regions of interest image area roi: pixel (0, 0) to pixel (2847, 2143) active area roi: pixel (8, 8) to pixel (2839, 2135) only the active area roi pixels are used for performance and defect tests. figure 13. regions of interest g b g r 2832 (h) 2128 (v) 4.7 m pixel g b g r g b g r 8 88 8 88 8 88 8 88 0,0 8,8 tests 1) dark field local non-uniformity floor (dsnu_flr) this test is performed under dark field conditions. a 4 frame average image is collected. this image is partitioned into 180 sub-regions of interest, each of which is 190 by 178 pixels in size. for each sub-region the standard deviation of all its pixels is calculated. the dark field local non-uniformity is the lar gest standard deviation found from all the sub regions of interest. units: e ? rms (electrons rms). 2) bright field local photoresponse non-uniformity (prnu_1) the sensor illuminated to 70% of saturation ( 700 dn). in this condition a 4 frame average image is collected. from this 4 frame average image a 4 frame average dark image is subtracted. the active area standard deviation is the standard deviation of the resultant image and the active area signal is the average of the resultant image. prnu_1 100 active area standard deviation active area signal units : % rms 3) bright field global non-uniformity (prnu_2) this test is performed with the sensor uniformly illuminated to 70% of saturation ( 700 dn), a 4 frame average image is collected and a 4 frame averaged dark image is subtracted. the resultant image is partitioned into 180 sub regions of interest, each of which is 190 by 178 pixels in size. the average signal level of each sub regions of interest (sub-roi) is calculated. the highest sub-roi average (maximum signal) and the lowest sub-roi average (minimum signal) are then used in the following formula to calculate prnu_2. prnu_2 100 max. signal min. signal active area signal units : % pp 4) dark field defect test this test is performed under dark field conditions. the sensor is partitioned into 390 sub regions of interest, each of which is 128 by 128 pixels in size. in each region of interest, the median value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the defect definition table section. 5) bright field defect test this test is performed with the imager illuminated to a level such that the output is at approximately 700 dn. the average signal level of all active pixels is found. the bright and dark thresholds are set as: dark defect threshold = active area signal ? threshold bright defect threshold = active area signal ? threshold the sensor is then partitioned into 390 sub regions of interest, each of which is 128 by 128 pixels in size. in each region of interest, the average value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of
kac?06040 www.onsemi.com 16 interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. example for bright field defective pixels: ? average value of all active pixels is found to be 700 dn ? lower defect threshold: 700 dn ? 12% = 84 dn ? a specific 128 128 roi is selected: ? median of this region of interest is found to be 690 dn. ? any pixel in this region of interest that is (690 ? 84 dn) in intensity will be marked defective. ? any pixel in this region of interest that is (690 ? 84 dn) in intensity will be marked defective. ? all remaining 299 sub regions of interest are analyzed for defective pixels in the same manner. 6) parasitic light sensitivity (pls) parasitic light sensitivity is the ratio of the light sensitivity of the photodiode to the light sensitivity of the storage node in global shutter. there is no equivalent distortion in rolling shutter. a low pls value can provide distortion of the image on the storage node by the scene during readout. pls photodiode responsivity storage node responsivity (unitlessratio) gse (global shutter efficiency) is a related unit. gse 1 1 pls % detailed method: photodiode responsivity: the sensor is set in global shutter serial mode (integration time not overlapping readout) and the flo signal is used to control a 550 nm normal incident (or large f# focused) illumination source so that the sensor is illuminated only during photodiode integration time (not illuminated during readout time). the integration time is not critical but should be large enough to create a measurable mean during this time. a 16 frame-average illuminated photodiode image is recorded. a 16 frame-average dark frame using the same sensor settings is captured and is subtracted from the illuminated image. detailed method: storage node responsivity: the sensor is set to a special characterization mode where the pd signal is discarded and does not impact the storage node. a long total frame time (storage node exposure time) is used to increase the storage node signal. a 16 frame-average dark frame is captured. the sensor is illuminated by the same 550 nm incident light source used for the photodiode responsivity. a 16 frame-average illuminated photodiode image is recorded; the dark frame image is subtracted from this. the integration time is not critical but should be set such that a significant response is detected, typically several orders of magnitude greater than the photodiode integration time. 7) black-sun anti-blooming a typical cmos image sensor has a light response profile that goes from 0 dn to saturation (1023 dn for kac?06040 in 10 bit adc mode) and, with enough light, back to 0 dn. the sensor reaching 0 dn at very bright illumination is often called the ?black-sun? artifact and is undesirable. black-sun artifact is typically the dominant form of anti-blooming image distortion. for the kac?06040 the black-sun artifact threshold is measured at the onset of saturation distortion, not at the point where the output goes to 0 dn. to first order the onset of black-sun artifact for the kac?06040 is not proportional to the integration time or readout time. the sensor is placed in the dark at unity gain and illuminated with a 532 nm laser with the intensity of about 26 w/cm 2 at the center of the sensor. the laser is strong enough to make the center of the laser spot below 1020 dn without any nd filters. nd filters are added to adjust the laser intensity until the signal in the region at the center of the spot increases to > 1020 dn. this illumination intensity at this nd filter is recorded (w/cm 2 ) as the black-sun anti-blooming. the ?xilumsat? unit is calculated using and integration time of 100 sec. exposing the sensor to very strong illumination for extended periods of time will permanently alter the sensor performance in that localized region. 8) read noise this test is performed with no illumination and one line of integration time. the read noise is defined as one standard deviation of the frequency histogram containing the values of all pixels after the excessively deviant pixels ( three standard deviations) are removed. 9) column noise after all rows are averaged together. shading (low frequency change wrt column address) is removed. a frequency histogram is constructed of the resulting column values. the column noise is the standard deviation of the frequency histogram of the column values. this metric includes both temporal and fpn. 10) row noise all columns are averaged together. shading (low frequency change wrt row address) is removed. a frequency histogram is constructed of the resulting row values. the row noise is the standard deviation of the frequency histogram of the row values. this metric includes both temporal and fpn. 11) maximum photoresponse non-linearity the photoresponse non-linearity is defined as the deviation from the best fit of the sensor response using 70% of saturation and zero signal as the reference points.
kac?06040 www.onsemi.com 17 the different signal levels are determined by varying the integration time. the sensor saturation level is (1023-dark offset). the dark offset is subtracted from the image for the following m av g and l av g . ? the integration time is varied until the integration time required to reach the 70% saturation is determined. m av g = the active array mean at the 70% saturation integration time. ? the integration is set to 1/14 (5% exposure point). l av g = meant at the 5% exposure point. ? prnl (@ 5% saturation) = ((l av g /m av g ) ? (14/1) ?1) ? 100 12) maximum gain difference between outputs the lvds outputs contain no gain or offset error since these are purely digital segmentations. the predominant output mismatch comes from the pixel array readout segmentation. the sensor contains two adc banks and four channels of analog line stores in its highest frame rate configuration, t ri?scan. the sensor is factory calibrated to match the gain differences between all four possible gain channels. the gain variations are manifest as an every 4 th row gain pattern. in tri?scan, and an even/odd row gain difference in dual?scan. the sensor is factory calibrated to match the four possible row gains. this test is performed in tri?scan mode to test the worst case gain error including all possible 4 row gains after the calibration has been applied. the sensor is illuminated at 70% of saturation. the entire test frame roi into 4 groups of every 4 th row. the first row group(average) is used as a reference and the following three row groups are compared to the first. the largest error is reported. second row average first row average 1 100 third row average first row average 1 100 fourth row average first row average 1 100 13) photodiode dark current the photodiode dark current is measured in rolling shutter read out mode using 105 ms integration time and an analog gain = 8. the value is converted to electrons/pix/sec using the formula: photodiode dark current aver. signal (dn) el?per?dn (gain=8) 0.105 seconds where ?average signal (dn)? is the average of all pixels in the sensor array, and ?el-per-dn (gain=8)? is measured on each sensor using the photon transfer method. 14) storage node dark current the storage node dark current is measured in global shutter read out mode using a special timing mode to prevent the photodiode dark current from being transferred to the storage node. in global shutter mode, the integration time of the storage node is the time it takes to read out a frame. the sensor analog gain is set to 2: storage node dark current aver. signal (dn) el?per?dn (gain=2) 0.138 seconds where ?average signal (dn)? is the average of all pixels in the sensor array and ?el-per-dn (gain=2)? is measured on each sensor using the photon transfer method. 15) lag lag is measured as the number of electrons left in the photodiode after readout when the sensor is illuminated at 70% of photodiode charge capacity. analog gain is set to 8. w ith no illumination a 64 average dark image is recorded (dark_ref). the ?el-per-dn? is measured using the photon transfer method. illumination is adjusted blink every other frame such that the mean image output is 70% of the photodiode charge capacity for even frames, and with no illumination for odd frames. a 64 frame average of odd dark frames is recorded as dark_lag. lag ( dark_lag dark_ref ) el?per?dn units : electrons rms 16) photodiode charge capacity the sensor analog gain is reduced to < 1 to prevent adc clipping at 1023 dn. the ?el-per-dn? is measured using the photon transfer method. the sensor is illuminated at a light level 1.5x the illumination at which the pixel output no longer linearly changes with illumination level. the photodiode charge capacity is equal to the average signal (dn) ? el-per-dn. units: electrons rms. 17) dark field faint column/row defect a 4 frame average, no illumination image is acquired at one line time of integration. major defective pixels are removed (> 5 sigma). all columns or rows are averaged together. the average of the local roi of 128 columns or rows about the column/row being tested is determined. any columns/rows greater than the local average by more than the threshold are identified. 18) bright field faint column/row defect a 4 frame average, 70% illumination image is acquired at one line time of integration. major defective pixels are removed (> 5 sigma). all columns or rows are averaged together. the average of the local roi of 128 columns or rows about the column/row being tested is determined. any columns/rows greater than the local average by more than the threshold are identified.
kac?06040 www.onsemi.com 18 19) total pixelized noise this test is performed with no illumination and one line of integration time. a single image is captured including both temporal and fixed pattern noise (fpn). a spatial low pass filter is applied to remove shading and excessively deviant pixels ( three standard deviations) are removed. the total pixelized noise is defined as one standard deviation of the frequency histogram. 20) responsivity ke ? /lux-sec this number is calculated by integrating the multiplication of the sensor qe by the human photopic response assuming a 3200k light source with a qt100 ir filter. this is a sharp 650 nm cutoff filter. if the ir filter is removed a higher response value will result. 21) responsivity v/lux-sec voltage levels are not output from the sensor. this value uses the pixel output before analog gain to match the adc input range. including the adc matching gain will result in a larger responsivity value. operation this section is a brief discussion of the most common features and functions assuming default conditions. see the kac?06040 user guide for a full explanation of the sensor operation modes, options, and registers. register address the last bit of any register address is a read/write bit. most references in this document refer to the w rite address. all spi reads are to an even address, all spi writes are to an odd address. sensor states figure 14 shows the sensor states, see the kac?06040 user guide for detailed explanation of the states. figure 14. sensor state diagram resetn low or reset reg 4060h reset standby config idle running wake?up (50 ms) <35 s <2 s <2 s 150 s running mode or trigger pin <50 s end of acquisition and idle mode and no trigger slave integration mode <50 s trig_wait <2 s end of acquisition readout trigger active edge ext_int trigger inactive edge
kac?06040 www.onsemi.com 19 encoded syncs to facilitate system acquisition synchronization the kac?06040 places synchronization words (sw) at the beginning and at the end of each output row as indicated in the following figure 15. this is performed for each of the 8 lvds output banks providing frame, line, and output synchronization. see the kac?06040 user guide for additional detail on lvds and encoded sync output. figure 15. encoded frame syncs v blanking period v blanking period data sol sof eol eof h blanking period line length (ll) line time this datasheet presumes the recommended startup script that is defined in the kac?06040 user guide has been applied. the kac?06040 defaults to dual?scan mode. in this mode the lvds data readout overlaps the pixel readout and adc conversion time. the pixel read time is fixed, and the adc conversion time is dependent on the adc bit depth selected. the lvds time will be dependent on the pll2 frequency selected. depending on the adc bit depth and the pll2 frequency the lvds readout or the (pixel + adc conversion) may limit the minimum possible line time. the line time is not impacted by the selection of rolling shutter or global shutter mode. tri?scan mode can be used in for shorter line times and faster frame rates (at elevated power consumption). tris?scan is of most value when the pixel time and adc conversion time and lvds readout time are similar in size. for full resolution this corresponds to 8 lvds bank and 10 bit adc bit depth. in t ri?scan mode the longest of the three components will define the minimum line time. the kac?06040 architecture always outputs two rows at once, one row from the top adc, and one from the bottom adc. each adc then divides up the pixel into 1 4 parallel pixel output lvds banks. the default is 4 output banks per adc for a total of 8 parallel pixel outputs to minimize the lvds data output time. since the sensor always outputs 2 rows at a time the timing and registers are based on a line time (lt) or line length (ll) where one lt = the time to readout 2 rows in parallel (one even row and one odd row). figure 16. dual?scan line time relationship 8 bank lvds output n pixel n+1 line n time = line length register (0200h) 10 bit adc n+1 line
kac?06040 www.onsemi.com 20 figure 17. tri?scan line time relationship 10 bit adc (n+1) 8 bank lvds (n) pixel (line n+2) min line time frame time the frame time is defined in units of line time. 1 line time unit = 2 output rows. to first-order the frame rate is not directly impacted by selection of global shutter, rolling shutter, dual-scan, or tri-scan. the frame time is made up of three phases: 1. integration phase 2. readout phase 3. frame wait phase (vertical blanking, v blank ) by default the integration phase overlaps the readout and frame w ait phases. if the integration phase is larger than the readout + frame w ait time, then the integration phase will determine the video frame rate. otherwise the frame rate will be set by the readout + frame w ait time. in other words, if the programmed integration time is larger than the minimum readout time (and vertical blanking) then extra vertical blanking will be added and the frame rate will slow to accommodate the requested integration time. figure 18. default frame time configuration (frame a) integration phase frame m integration phase frame m+1 integration phase frame m+2 readout phase frame m readout phase frame m+1 frame wait frame wait video frame time = readout + wait if the integration phase is less than the readout phase then the start of integration is automatically delayed to minimize the storage time and dark current. figure 19. frame time with extended integration time integration phase frame m+2 readout phase frame m+1 frame wait video frame time = integration time integration phase frame m+1 readout phase frame m frame wait integration phase frame m if the readout phase (+ v blanking ) is less than the integration phase, then the readout occurs as soon the integration is complete to minimize the storage time and dark current. see the kac?06040 user guide for detailed calculation of the integration phase, readout phase, and frame wait. to first-order the readout phase is equal to the number of rows ? row_time.
kac?06040 www.onsemi.com 21 global shutter readout global shutter readout provides the maximum precision for freezing scene motion. any motion artifacts will be 100% defined by an ideal integration time edge. every pixel in the array starts and stops integration at the same time. figure 20 illustrates a global shutter frame readout assuming the recommended start-up script defined in the kac?06040 user guide (8 lvds banks, dual-scan, 8.75 s line time). the frame wait phase is not shown due to its small default size (1 ll) and for clarity. figure 20. illustration of frame time for global shutter readout integration time integration of next frame overlaps readout of previous frame frame readout effective frame time (video) = readout time trigger pin: true time/col address axis row address axis global shutter readout mode is selected using bits [1:0] of register 01d1h. images can be initiated by setting and holding the trigger input pin or by placing the sensor into running mode by writing 03d to register 4019h. if the trigger input pin is true when at the start of the integration time for the next frame then the sensor will complete an additional frame integration and readout. in the case shown in figure 20 two frames will be output.
kac?06040 www.onsemi.com 22 rolling shutter readout the kac?06040 high speed rolling shutter readout provides the maximum dynamic range while still providing excellent motion capture. in rolling shutter the readout more closely matches a film camera shutter. each row of the image receives the same integration time, but each row starts and ends at a different time as the shutter travels from the top of the array to the bottom. in the figure 21 frame time illustration this ?moving shutter? displays as a sloped edge for the blue pixel array region, just as the readout edge is sloped. the figure 21 illustration shows a 2 frame output sequence using the external trigger pin. figure 21. illustration of frame time for rolling shutter readout integration time integration of next frame overlaps readout of previous frame frame readout effective frame time (video) = readout time trigger pin: true time/col address axis row address axis rolling readout mode can be selected using bits [1:0] of register 01d1h. images can be initiated by setting and holding the trigger input pin or by placing the sensor into running mode by writing 03d to register 4019h. if the trigger input pin is true when at the start of the integration time for the next frame then the sensor will complete an additional frame integration and readout.
kac?06040 www.onsemi.com 23 8 bank lvds data readout lvds banks the kac?06040 provides 8 parallel pixel banks, each consisting of 8 l vds differential pairs (7 data pairs + 1clock pair). this allows the output of 8 pixels per lvds clock period. all 7 data pairs, of each bank, are used only in 14 bit operation mode. by default only 5 data pairs are used for 10 bit mode (d4 d0). the unused pairs are held in low-power high impedance mode. figure 22. lvds bank labeling pixel array 2 bank mode bank 3 bank 5 bank 7 bank 2 bank 4 bank 6 bank 0 bank 1 pixel array 4 bank mode bank 3 bank 5 bank 7 bank 2 bank 4 bank 6 bank 0 bank 1 pixel array 8 bank mode bank 3 bank 5 bank 7 bank 2 bank 4 bank 6 bank 0 bank 1 the number of output banks used is independent of the adc bit depth chosen. by default the kac?06040 uses all 8 output banks for maximum frame rate. if technical restrictions prevent the use of 8 l vds banks, the sensor can be programmed to use 4 or 2 banks, however this can result in reduced frame rate and reduction of image quality. it is recommended that 8 banks be used when possible. only the 8 bank option is discussed in detail in this specification, see the kac?06040 user guide for additional detail on 4 and 2 bank mode. in order to minimize the lvds clock rate (and power) for a given data rate the pixels are output in ddr (double data rate) where the msb is always sent first (on rising edge) and the lsb second (falling edge) this is not programmable. ports per lvds bank the msb comes out first on the falling edge, followed by the lsb on the net rising edge. table 13. number of lvds pairs (ports) used vs. bit depth bit depth edge of data clk data0 data1 data2 data3 data4 data5 data6 14 bits falling (msb nibble) d7 d8 d9 d10 d11 d12 d13 rising (lsb nibble) d0 d1 d2 d3 d4 d5 d6 12 bits falling (msb nibble) d6 d7 d8 d9 d10 d11 hiz rising (lsb nibble) d0 d1 d2 d3 d4 d5 hiz 10 bits falling (msb nibble) d5 d6 d7 d8 d9 hiz hiz rising (lsb nibble) d0 d1 d2 d3 d4 hiz hiz 8 bits falling (msb nibble) d4 d5 d6 d7 hiz hiz hiz rising (lsb nibble) d0 d1 d2 d3 hiz hiz hiz
kac?06040 www.onsemi.com 24 8 bank pixel order the kac?06040 always processes two rows at a time. even row decodes are sent to the bottom adc and lvds output banks (0, 2, 4, 6). odd rows are sent to the top adc and lvds banks (1, 3, 5, 7). the roi must be (and is internally forced to) an even size and always starting on an even row decode. the rows are read out progressively left to right (small column address to large). eight pixels are sent out of the chip at once, one pixel per lvds bank per lvds clock cycle. pixel readout order: 1. two rows are selected, the even row is sent to the bottom adc and the odd row to the top adc. 2. each adc converts its row of pixel data at once and stores the result in a line buffer. 3. at default settings there are 4 output lvds banks for each adc. 4. each lvds bank outputs one pixel per clock cycle, so 4 pixels of each row are output each full lvds clock cycle, two rows in parallel for 8 pixels per clock cycle total. 5. the pixels are sent out from left to right (low column number to high column number). so the first 4 pixels are sent out on clock cycle 1, and the next 4 pixels to the right are sent out on clock cycle 2. 6. to conserve the number of wires per port, the 10 bits per pixel are sent out ddr (dual data rate) over 5 ports. on the falling edge the upper 5 msb bits are sent out, and on the rising edge the lower 5 bits lsb are sent out. completing one full lvds clock cycle and one set of eight pixels. figure 23. pixel readout order diagram bank 0 bank 1 row 2n +1 row 2n first clk?data pulse second clk?data pulse 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 bank 2 bank 4 bank 6 bank 3 bank 5 bank 7 table 14. pixel readout order table lvds bank row pixel number bank 0 2n (even) 0 4 8 12 16 bank 2 2n (even) 1 5 9 13 17 bank 4 2n (even) 2 6 10 14 18 bank 6 2n (even) 3 7 11 15 19 bank 1 2n+1 (odd) 0 4 8 12 16 bank 3 2n+1 (odd) 1 5 9 13 17 bank 5 2n+1 (odd) 2 6 10 14 18 bank 7 2n+1 (odd) 3 7 11 15 19 lvds clock cycle 1 2 3 4 5
kac?06040 www.onsemi.com 25 de-serializer settings figure 24 shows the data stream of one lvds bank for 10 bit resolution. data serialization is fixed at 2 cycle ddr for all bit depths. data output order is msb first on the falling edge, and lsb following on the rising edge. four pixel values per synchronization word are embedded into the video stream per lvds bank. the sol/sof synchronization words are sent out of each lvds bank before the first valid pixel data from that bank. each bank outputs all 4 syncs of the sof or sol. and each of the active lvds banks each output all 4 sync codes for the eol/eof. figure 24. data stream of one lvds bank for 10 bits adc resolution sw1 dclk0 data0 data1 data2 data3 data4 d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 msb lsb msb d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 msb lsb msb d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 lsb msb d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 lsb msb d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 lsb msb d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 lsb msb d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 lsb msb d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 lsb msb d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 lsb msb d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 lsb msb d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 lsb msb d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 lsb msb d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 lsb msb d3 d0 d1 d2 d4 d8 d5 d6 d7 d9 lsb msb d3 d0 d1 d2 d4 lsb d3 d0 d1 d2 d4 lsb d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 msb lsb d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 msb lsb d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 msb lsb d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 msb lsb d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 msb lsb d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 msb lsb d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 msb lsb d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 msb lsb d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 msb lsb d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 msb lsb d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 msb lsb d8 d5 d6 d7 d9 d3 d0 d1 d2 d4 msb lsb sw2 sw3 sw4 p0 p1 p2 p3 sw1 sw2 sw3 sw4 pn?1 pn synchronized word on 10 bits data on 10 bits t synchronized word on 10 bits
kac?06040 www.onsemi.com 26 register definition table 15. register definition 16 bit address (hex) reset value hex/dec spi state register name 0001 0d any frame a roi y1 0009 2144d any frame a roi h1 0011 0d any frame a roi x1 0019 2848d any frame a roi w1 0021 0d any frame a sub-roi y2 0029 0d any frame a sub-roi h2 0031 0d any frame a sub-roi x2 0039 0d any frame a sub-roi w2 0041 0d any frame a sub-roi y3 0049 0d any frame a sub-roi h3 0051 0d any frame a sub-roi x3 0059 0d any frame a sub-roi w3 0061 0d any frame a sub-roi y4 0069 0d any frame a sub-roi h4 0071 0d any frame a sub-roi x4 0079 0d any frame a sub-roi w4 0081 0011h any frame a decimation 0089 0d any frame a video blanking 0091 3430d any frame a integration rows 0099 0d any frame a integration sub?row 00a1 10d any frame a black level 00a9 001fh any frame a gain 00e9 344d any frame b roi y1 00f1 1456d any frame b roi h1 00f9 136d any frame b roi x1 0101 2576d any frame b roi w1 0109 0d any frame b sub-roi y2 0111 0d any frame b sub-roi h2 0119 0d any frame b sub-roi x2 0121 0d any frame b sub-roi w2 0129 0d any frame b sub-roi y3 0131 0d any frame b sub-roi h3 0139 0d any frame b sub-roi x3 0141 0d any frame b sub-roi w3 0149 0d any frame b sub-roi y4 0151 0d any frame b sub-roi h4 0159 0d any frame b sub-roi x4 0161 0d any frame b sub-roi w4 0169 0011h any frame b decimation 0171 0d any frame b video blanking 0179 3430d any frame b integration rows 0181 0d any frame b integration sub?row 0189 10d any frame b black level 0191 001fh any frame b gain
kac?06040 www.onsemi.com 27 table 15. register definition (continued) 16 bit address (hex) reset value hex/dec spi state description 01d1 fc10h config only config1 01d9 0500h config or idle config2 01e1 00aah config or idle analog/digital power mode 01e9 0000h config or idle dual-video repetition 01f1 0d config or idle vertical blanking 01f9 3431d config or idle fixed frame period 0201 1400d config or idle line length (ll) 0209 002dh config or idle adc bit depth 0211 0000h config or idle flo edge delay 0219 0000h config or idle mso edge delay 0708 0000h any sensor type fb 0710 0000h any temperature sensor fb 0718 0000h any general feedback 0720 0000h any minimum ll fb 0730 0000h any user otp1 fb 0738 0000h any user otp2 fb 2059 0300h config only output bank select 1 2099 2877h config only pll1 setting 20a1 0861h config only pll2 setting 2449 1c32h config only sub-lvds enable 2479 10b8h any bsc clamp threshold a 2481 20c7h any bsc clamp threshold b 2499 0000h config or idle test pattern control 1 24a1 536d config or idle test pattern control 2 24b9 202d config only companding slope 1 length 24c1 101d config only companding slope 2 length 24c9 101d config only companding slope 3 length 24d1 101d config only companding slope 4 length 24d9 101d config only companding slope 5 length 24e1 420d config only companding slope 6 length 24e9 0083h config only companding slope 1/2 gain 24f1 038fh config only companding slope 3/4 gain 24f9 0fbfh config only companding slope 5/6 gain 2501 1f9fh config only companding slope 7 gain 2559 7804h any defect avoidance threshold 2561 003fh any defect avoidance enable 25c1 0003h config or idle encoded sync config 2619 000bh config only output bank select 2 4000 4100h any chip revision code 4008 0011h any chip id code msb 4010 0080h any chip id code lsb 4019 0000h any set sensor state 4021 0000h config or idle otp address
kac?06040 www.onsemi.com 28 table 15. register definition (continued) 16 bit address (hex) description spi state reset value hex/dec 4029 0000h config or idle otp write data 4031 0000h config or idle command_done_fb 4041 0000h config or idle otp read data 4061 0000h config or idle soft reset notes: spi state (the sensor state from which the register can be set): 1. ?any?: can be written from any state (including running). 2. ?config or idle?: these registers can be changed in idle or config states. 3. ?config only?: sensor must be in config state to set these registers. 4. only register 4018h and 4060h may be set when the sensor is in standby state. 5. fb = feedback, a read?only register that provides some error or status. notes: decimal, hexadecimal, binary values: 1. ?b? denotes a binary number, a series of bits: msb is on the left, lsb is on the right. 2. ?h? or ?hex? denotes a hexadecimal number (base 16, 1?9, a?f). the letters in a hex number are always capitalized. 3. ?d? denotes a decimal number. 4. note that ?0? and ?1? are the same value in all number base systems and sometimes the base notation is omitted. the kac?06040 features an embedded microprocessor by cortus.
kac?06040 www.onsemi.com 29 absolute maximum ratings for supplies and inputs the maximum rating is defined as a level or condition that should not be exceeded at any time. if the level or the condition is exceeded, the device will be degraded and may be damaged. operation at these values will reduce mean time to failure (mttf). table 16. supplies description value avdd_lv, vdd_dig ?0.25 v; 2.3 v avdd_hv, vref_p, vdd_lvds ?0.25 v; 4 v dc input voltage at any input pin ?0.25 v; vdd_dig + 0.25 v table 17. cmos inputs parameter symbol minimum typical maximum unit input voltage low level v il ?0.3 ? 0.35 vdd_dig v input voltage high level v ih 0.65 vdd_dig ? vdd_dig + 0.3 v
kac?06040 www.onsemi.com 30 operating ratings table 18. input clock conditions parameter minimum typical maximum unit frequency for clk_in1 and clk_in2 5 48 50 mhz duty cycle for clk_in1 and clk_in2 40 50 60 % resetn 10 ? ? ns trigger pin minimum pulse width 20 ? ? ns trigger must be active at least 4 periods of pll1 ( 12.5 ns at 320 mhz) to start a capture cycle. the polarity of the active level is configurable by spi (register 01d8h bit 0), the default is active high (i.e. pin = vdd_dig = trigger request). table 19. operating temperature description symbol minimum maximum unit operating temperature (note 1) t op ?40 80 c 1. under conditions of no condensation on the sensor. table 20. cmos in/out characteristics parameter symbol minimum typical maximum unit output voltage low level v ol ? ? 0.45 v output voltage high level v oh vdd_dig ? 0.45 ? ? v input hysteresis voltage v th ? 0.25 ? pull-up resistor value for resetn pin r pu 62 ? ? k pull-down resistor value for trigger pin r pd 100 ? ? k current on adc_ref pin i adc_ref ? 100 ? a
kac?06040 www.onsemi.com 31 table 21. supplies parameter symbol minimum typical maximum unit lvds io supply vdd_lvds 3.15 3.30 3.63 v pixel high voltage supply avdd_hv 3.40 3.50 3.60 v pixel low voltage supply vref_p 2.71 2.80 2.88 v analog power supply avdd_lv 1.71 1.80 1.89 v digital power supply vdd_dig 1.90 2.00 2.10 v avdd_hv ? vref_p ? 0.5 ? v power in standby state ? 10 ? mw current in standby state vdd_lvds avdd_hv avdd_lv vref_p vdd_dig ? ? ? ? ? < 0.5 < 0.5 < 0.5 < 0.5 1 ? ? ? ? ? ma power in config state ? 320 ? mw current in config state vdd_lvds avdd_hv avdd_lv vref_p vdd_dig ? ? ? ? ? < 0.5 < 0.5 < 0.5 < 0.5 162 ? ? ? ? ? ma power in idle state ? 510 ? mw current in idle state vdd_lvds avdd_hv avdd_lv vref_p vdd_dig ? ? ? ? ? < 0.5 20 < 0.5 < 0.5 222 ? ? ? ? ? ma power in running state ? 2.26 ? w current in running state vdd_lvds in sub-lvds mode avdd_hv avdd_lv vref_p vdd_dig ? ? ? ? 115 100 20 20 721 ? ? ? ? ma 1. voltages relative to vss. current measurements made in darkness. 2. max frame rate (and thus maximum current mode). a. tri0scam mode b. 10 bit adc c. pll2 = max spec mhz d. no horizontal or vertical blanking and 8 active lvds banks.
kac?06040 www.onsemi.com 32 spi (serial peripheral interface) the spi communication interface lets the application system to control and configure the sensor. the sensor has an embedded slave spi interface. the application system is the master of the spi bus. table 22. name sensor i/o direction description csn i spi chip select ? active low, this input activates the slave interface in the sensor. sck i spi clock ? toggled by the master. miso o spi master serial data input ? slave (sensor) serial data output. mosi i spi master serial data output ? slave (sensor) serial data input. table 23. parameter minimum typical maximum unit spi sck 5 25 50 mhz duty cycle on spi sck 40 50 60 % clock polarity and phase cpol (clock polarity) and cpha (clock phase) are commonly defined in spi protocol such as to define sck clock phase and polarity. the kac?06040 defaults to expecting the master to be configured with cpol = 1 (the base value of the clock is vdd_dig) and cpha = 1 (data is valid on the clock rising edge). figure 25. cpol = 1 and cpha = 1 configuration csn sck mosi miso x x x x ? ? ? ?
kac?06040 www.onsemi.com 33 spi protocol figure 26. spi write byte order csn msb sclk mosi lsb msb lsb 16 bit address word 16 bit data to write byte 0 byte 1 byte 2 byte 3 8 cycles 8 cycles 8 cycles 8 cycles figure 27. spi read byte order csn msb sclk mosi lsb msb lsb 16 bit address word 16 bit read data byte 0 byte 1 byte 2 byte 3 8 cycles 8 cycles 8 cycles 8 cycles miso wait time 1.5 s there is a delay during readback between presenting the address to be read on the mosi and being able to read the register contents on the miso. this delay is not the same for all registers. some are available immediately, some require a longer fetch time. the 1.5 s shown in figure 27 is the maximum time to fetch a register?s value when in config state (the recommended state for changing registers). some registers can be adjusted during running state (see the register summary on page 26). if performing a readback during running state, the delay could be as long as 4.5 s depending on when in the row the request was sent and the sensor?s microcontroller activity at that moment. the spi fb pin can be used to dynamically adjust the wait time for a register contents to be fetched. figure 29 illustrates the use of the fb pin. the fb output will be low (vss) until the requested register contents are ready to be clocked out of the mosi pin. once the fb pin goes high (vdd_dig) then clocking the sclk will transmit the requested register contents. the spi fb pin is inactive by default, this function is enabled in register 4041h.
kac?06040 www.onsemi.com 34 figure 28. spi read with fbrb handshaking csn msb sclk mosi lsb msb lsb 16 bit address word 16 bit read data byte 0 byte 1 byte 2 byte 3 8 cycles 8 cycles 8 cycles 8 cycles miso variable wait time fb the note that readback does not provide the actual register value being used, but reflects the next value to be used. all new register writes are placed in a shadow memory until they can be updated into the active memory. this active memory update occurs at the start of the next frame or upon entering the state listed in the register summary table on page 26. register reads access this shadow memory not the active memory. for instance if the sensor is in running mode and you adjust the ll in register 200h. you can read back and confirm that your register change was received by the sensor; however, the ll will not change since register 200h can only be changed in config state. if you change the sensor state to config and then back to running, then the new ll will take effect.
kac?06040 www.onsemi.com 35 spi interface figure 29. spi timing chronogram msb msb?1 x msb t cs_setup t cycle t cs_hold t hold t setup t out_delay t out_delay_csn ? ? cs sck mosi miso table 24. spi timing specification symbol minimum value maximum value unit t cycle 25 ns t setup 2.9 ns t hold 0.8 ns t cs_setup 12.5 ns t cs_hold 12.5 ns t out_delay_csn 3.1 4.7 ns t out_delay 4.9 8.7 ns
kac?06040 www.onsemi.com 36 lvds interface the data output can be configured to follow standard tia/eia?644?a lvds specification or a low power mode compatible with common sub-lvds definition used in fpga industry. (please refer to the kac?06040 user guide for more information). unless otherwise noted, min/max characteristics are for t = ?40 c to +85 c, output termination resistance rl = 100 1%, typical values are at vdd_lvds = 3.3 v. use register 2449h to select standard or sub-lvds. this document assumes that sub-lvds is active for all power measurements. standard lvds can increase the average power consumption as much as 200 mw in the case of minimum horizontal and vertical blanking. table 25. standard lvds characteristics parameter symbol minimum typical maximum unit differential output voltage vod 250 355 450 mv vod variation between complementary output states vod ?20 ? 20 mv common mode output voltage vocm 1.235 1.259 1.275 v vocm variation between complementary output states vocm ?25 ? 25 mv high impedance leakage current iozd ?1 ? 1 a output short circuit current: when d+ or d? connected to ground when d+ or d? connected to 3.3 v iosd 2.9 12.25 ? ? 4.3 30.47 ma output capacitance cdo ? 1.3 ? pf maximum transmission capacitance load expected (for 260 mhz lvds clock) ? ? 10 pf table 26. sub-lvds characteristics parameter symbol minimum typical maximum unit differential output voltage v od 140 180 220 mv vod variation between complementary output states v od ?5 ? 5 mv common mode output voltage v ocm 0.88 0.90 0.92 v vocm variation between complementary output states v ocm ?10 ? 10 mv high impedance leakage current i ozd ?1 ? 1 a output short circuit current: when d+ or d? connected to ground when d+ or d? connected to 3.3 v i osd 1.4 10.21 ? ? 2.2 30.47 ma output capacitance c do ? 1.3 ? pf maximum transmission capacitance load expected (for 260 mhz lvds clock) ? ? 10 pf table 27. parameter minimum typical maximum unit lvds_clk 50 160 160 mhz duty cycle on lvds_clk ? 50 ? %
kac?06040 www.onsemi.com 37 in-block lvds timing specification the table below gives lvds timing specification for one group of lvds for nominal frequency of 260 mhz. there is no skew specification between groups. table 28. in-block lvds timing specification parameter symbol value typical maximum unit minimum time between data change and clock rising edge ts dlh 600 ? ? ps minimum time between clock rising and data change th dlh 600 ? ? ps minimum time between data change and clock falling edge ts dhl 600 ? ? ps minimum time between clock falling edge and data change th dhl 600 ? ? ps maximum differential skew between the 7 data pairs t skd ? 200 700 ps figure 30. lvds timing chronogram ts dlh v oh v ol differential data differential clock ts dhl th dlh th dhl table 29. inter-block lvds timing specification parameter minimum typical maximum unit inter-block skew ? 6 12 lvds clock periods
kac?06040 www.onsemi.com 38 storage and handling table 30. storage conditions description symbol minimum maximum unit notes storage temperature t st ?40 80 c 1 humidity rh 5 90 % 2 1. long-term storage toward the maximum temperature will accelerate color filter degradation. 2. t = 25 c. excessive humidity will degrade mttf. for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for information on soldering recommendations, please download the soldering and mounting techniques reference manual (solderrm/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com .
kac?06040 www.onsemi.com 39 mechanical information completed assembly figure 31. completed assembly (1 of 5) 1. see ordering information for marking code. 2. no materials to interfere with clearance through package holes. 3. imaging array is centered at the package center. 4. length dimensions in mm units. notes:
kac?06040 www.onsemi.com 40 figure 32. completed assembly (2 of 5)
kac?06040 www.onsemi.com 41 figure 33. completed assembly (3 of 5)
kac?06040 www.onsemi.com 42 figure 34. completed assembly (4 of 5) figure 35. completed assembly (5 of 5)
kac?06040 www.onsemi.com 43 mar (multi-layer anti-reflective coating) cover glass figure 36. mar cover glass specification 1. units: in [mm] 2. a-zone dust/scratch spec: 10 m maximum 3. index of refraction: 1.5231 notes: on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 kac?06040/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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